1. Field of the Invention
This invention relates in general to computer architectures, and, more particularly, to a method and an apparatus for enabling indirect addressing and lookup table implementation on Single Instruction stream Multiple Data stream (SIMD) multi-processor architectures.
2. Description of the Related Art
In existing SIMD computer architectures, memory is generally accessed by the processor array as a single plane of memory locations.
In conventional SIMD architectures, the memory address location is broadcast, along with the instruction word, to all processing elements by the controller. This configuration normally results in the processing elements accessing a single plane of data in memory. Offsets from this plane of data cannot be done using this architecture, as there is no provision for specifying, or modifying, the local memory address associated with each processor based on local data in each processor.
As a consequence of this lock-step approach, it is especially difficult to implement efficiently indirect addressing and look-up tables in a parallel processing architecture following the Single Instruction stream Multiple Data stream execution paradigm. Indirect addressing requires serialization of operations and thus uses O(N) cycles to perform the memory access in an N processor system.